COMPLETE LEARNING PATH · 18 CHAPTERS
Goal: independently complete a small digital chip
The course has two connected tracks. Chapters 1-12 establish manufacturing, packaging, memory, and industry constraints. Chapters 13-18 use one streaming accelerator project to complete specifications, SystemVerilog RTL, verification, synthesis, STA, physical design, and tapeout review.
TRACK 01
Manufacturing Foundations
Chapter 1
Semiconductor Manufacturing Overview
From silicon wafer to advanced GPU package
Chapter 2
Wafer Fabrication Flow
How deposition, lithography, etching, doping, CMP, and metrology repeat
Chapter 3
Lithography, DUV, and EUV
The engineering of printing circuit patterns onto wafers
Chapter 4
Transistor Process, FinFET, and GAAFET
From planar MOSFETs to fins and nanosheets
Chapter 5
Interconnect and RC Delay
When transistors get faster, wires and power delivery become bottlenecks
Chapter 6
Advanced Packaging, CoWoS, and Chiplets
Turning multiple dies into one high-bandwidth system
Chapter 7
HBM, TSV, and Memory Bandwidth
Why advanced GPUs depend on stacked DRAM
Chapter 8
Advanced GPU Manufacturing and Integration
How logic dies, HBM, packaging, and system validation become a product
Chapter 9
Yield, Testing, and Binning
Why chips from the same wafer are not all equal
Chapter 10
Semiconductor Supply Chain
How equipment, materials, foundry, OSAT, memory, and systems fit together
Chapter 11
What Is Cerebras and Why It Matters for AI Chips
Understanding another AI accelerator path through wafer-scale WSE design
Chapter 12
NVIDIA, Cerebras, and Google TPU Compared
Comparing general GPUs, wafer-scale systems, and matrix-focused ASICs
TRACK 02 · PROJECT BASED
Practical Chip Design: Specification to GDS
All six chapters advance one design, with engineering deliverables and exit criteria at every stage.
Chapter 13 · 4-6 hours
Requirements to Chip Architecture
Define interface contracts, registers, widths, and PPA budgets
Chapter 14 · 8-12 hours
Implement RTL in SystemVerilog
Build the FSM, datapath, handshakes, reset, and CDC boundaries
Chapter 15 · 10-16 hours
Verification: Prove the RTL
Reference models, random stimulus, assertions, coverage, and regression
Chapter 16 · 8-12 hours
Synthesis and Static Timing
Map standard cells, constrain clocks and I/O, analyze setup and hold
Chapter 17 · 12-20 hours
Physical Design: Netlist to Layout
Floorplan, power, placement, CTS, routing, and signoff
Chapter 18 · Final review
Tapeout Readiness and Independent Project
Freeze the release, plan silicon bring-up, and design your own chip