What interconnect means
After transistors perform switching, multilayer metal wires connect standard cells, SRAM, caches, control logic, and IO. Local wires are narrow, global wires are wider, and the power grid must distribute large currents across the die. Low-k dielectrics are used to reduce wire-to-wire capacitance.
RC delay and congestion
Shrinking wire width raises resistance, while tighter spacing raises coupling capacitance. The result is RC delay and signal-integrity pressure. At advanced nodes, interconnect delay often does not improve with transistor scaling, and routing congestion, IR drop, electromigration, and hotspots can limit frequency.
Why GPUs care
A GPU contains many SIMD arrays, register files, L2 cache slices, and NoC or crossbar communication paths. Even if arithmetic units are abundant, on-die interconnect and power delivery can limit real performance through data movement, synchronization, and power walls.