Physical Design: Netlist to Layout

Floorplanning sets the ceiling

Choose die and core size, utilization, aspect ratio, I/O locations, macro placement, and power topology. Excessive utilization creates congestion and leaves no room for buffers; too little increases wire length and cost. A small standard-cell-only design can begin near 50-60% core utilization and adjust from congestion reports. Group I/O by data flow rather than placing pins arbitrarily.

Power planning includes rings, straps, rails, and vias. Correct logic can still fail from resistive IR drop, simultaneous switching noise, or long-term electromigration. Treat power integrity as its own signoff dimension even when an educational PDK provides only limited analysis.

Placement, CTS, and routing

Placement assigns cells to legal rows while optimizing timing, wire length, and congestion. Clock-tree synthesis inserts buffers to control skew and insertion delay; the clock is no longer ideal afterward. Routing assigns real metal layers and vias, adding parasitic resistance and capacitance that can consume synthesis-stage timing margin.

Check timing, transition, capacitance, legality, and congestion after every stage. Diagnose whether a bad path comes from architecture, constraints, placement, or routing before applying an optimization. Higher tool effort is not a substitute for understanding the root cause.

Signoff asks different questions

• DRC: does layout geometry satisfy foundry width, spacing, enclosure, and manufacturing rules?
• LVS: does the circuit extracted from layout match the intended netlist?
• STA: do all valid paths meet setup and hold with extracted parasitics across required PVT corners?

Also review antenna, density, IR drop, electromigration, and power. Open educational flows may cover only part of production signoff, so document exactly what was and was not checked.

Chapter deliverables

• A floorplan image and rationale for die/core, utilization, I/O, and power choices.
• Placement, CTS, and routing QoR: area, congestion, wire length, WNS, and TNS.
• Final GDS, DEF, extracted netlist, SPEF, timing reports, and logs.
• DRC/LVS results with a reason for every waiver.