Synthesis and Static Timing Analysis

What synthesis produces

Synthesis converts RTL, a cell library, and design constraints into a gate-level netlist. The same RTL can produce different circuits under different clocks, corners, and objectives. Before optimization, inspect elaborated hierarchy, parameters, inferred memories, latches, multiple drivers, unmapped cells, and disconnected ports. Reported cell area is not final die area.

read_liberty -lib sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog stream_accel.v
hierarchy -check -top stream_accel
synth -top stream_accel
dfflibmap -liberty sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib
write_verilog netlist/stream_accel.v

Constraints express design intent

STA needs clock period and waveform, input arrival times, output requirements, uncertainty, and justified timing exceptions. An unconstrained path has not passed; it was simply never checked. At 100 MHz the nominal period is 10 ns, but uncertainty, clock insertion, and external interfaces consume part of that budget.

create_clock -name core_clk -period 10.0 [get_ports clk]
set_clock_uncertainty 0.20 [get_clocks core_clk]
set_input_delay  1.50 -clock core_clk [get_ports {in_* start_pulse}]
set_output_delay 1.50 -clock core_clk [get_ports {out_* busy irq}]
set_false_path -from [get_ports rst_n]

Every false path or multicycle path needs a structural reason and review record. Timing exceptions must not be used to hide negative slack.

Read setup, hold, and critical paths

Setup checks that data arrives early enough before the next capture edge; hold checks that it remains stable after the current edge. Setup failures may need a lower clock, less logic depth, pipelining, or faster cells. Hold is largely independent of clock period and is normally repaired by adding delay. Positive slack is margin; negative slack is a failure.

The 40-bit adder may become this design's critical path. Confirm constraints and inspect the full path before changing RTL. Adding a pipeline stage changes latency and control behavior, so it must return through specification and verification.

Chapter deliverables

• Reproducible synthesis scripts, netlist, area, and cell-usage reports.
• An SDC file with zero unconstrained endpoints.
• Explanations for the ten worst setup and hold paths.
• RTL-to-netlist equivalence or a documented gate-level smoke test.