From Product Requirements to Chip Architecture

Choose the right first chip

A first independent design should not be a CPU or an AI training accelerator. It should have the boundaries of a real chip while keeping the internal logic small enough to understand: clock and reset, a control bus, configuration registers, a datapath, a state machine, storage, errors, and an interrupt. Our project is a programmable streaming accumulator. Software writes its control registers, a stream of 32-bit samples enters through a valid/ready interface, and a 40-bit sum leaves through another handshake interface.

Freeze measurable targets before writing RTL: batch lengths from 1 to 256, one accepted sample per cycle, a 100 MHz target clock, synchronous active-low reset, one clock domain, and correct behavior under arbitrary input bubbles and output backpressure. Record area and power, but do not optimize aggressively until a correct baseline has been synthesized.

Write interface contracts, not descriptions

Every interface entry must define direction, width, sampling edge, idle value, reset behavior, backpressure, and error handling. A valid/ready transfer occurs only on a rising edge where both signals are high. A producer must hold valid and data stable while stalled; it must not wait for ready before asserting valid. These rules are directly testable.

input  logic        in_valid;
output logic        in_ready;
input  logic [31:0] in_data;
output logic        out_valid;
input  logic        out_ready;
output logic [39:0] out_sum;

Define CONTROL, LENGTH, STATUS, and RESULT registers. For each bit specify access type (RW, RO, or W1C), reset value, side effects, and behavior for illegal writes. The register map is a shared contract between RTL, firmware, and verification.

Build quantitative budgets

Track throughput, latency, storage, and width. One 32-bit sample per cycle at 100 MHz gives a peak input rate of 400 MB/s. A batch of N samples needs at least N successful handshakes plus control and output latency. Streaming accumulation avoids buffering the entire batch. The worst-case unsigned sum needs 40 bits because 32 + log2(256) = 40.

Performance, power, and area trade against each other. Parallel adders improve throughput but cost cells, routing, and switching power. A lower clock relaxes timing but increases task duration. Start with the architecture that is easiest to prove correct, then optimize from actual synthesis and timing reports.

Chapter deliverables

• A block diagram covering APB registers, control FSM, accumulator datapath, and interrupt logic.
• Port and register tables with cycle-accurate handshake and reset rules.
• At least ten verifiable requirements, including behavior for start while busy.
• Initial PPA targets, process-library assumptions, and an explicit out-of-scope list.